1. Field of the Invention
The present invention relates to processes involved in the manufacturing and testing of semiconductor devices. More particularly, the present invention relates to methods for testing semiconductor electronic devices.
2. Description of the Related Art
As integrated circuit devices grow smaller and smaller, the testing of the integrated circuits presents greater challenges. For example, the shrinkage of transistor sizes to the point that critical dimensions are well below one micron (10−6 m) has compelled designers to reduce operating voltages to maintain device reliability. And while designers enjoy a significant improvement in device speeds due to the smaller geometries employed, it has not been possible to reduce power consumption in direct relation to those critical dimensions. As a result, device currents have tended to increase, which has forced designers to employ ever-greater amounts of ingenuity to the problem of distributing the total current available to the designed devices.
Semiconductor wafer fabrication involves a series of processes used to create semiconductor devices and integrated circuits (IC's) in and on a semiconductor wafer surface. Fabrication typically involves the basic operations of layering and patterning, together with others such as doping, and heat treatments. Typically, a large number of dies are formed on a wafer using these methods. Many of these dies may have defects occurring during the fabrication process, for example during the patterning of layers, which affect the reliability of the die. Some defects, for example, directly affect the functionality of the circuit resulting in functional failure. Other defects may adversely affect the reliability of the circuit resulting in an early lifetime failure or failure under varying operating conditions.
Some conventional testing methods for identifying defects measure current in a device. When a device draws a large amount of current, this condition can have a variety of causes: some benign, and some far less so. That is, normal process variations may produce natural variations in device electrical characteristics that make differentiation of good die from defective die difficult. For example, current measured in a CMOS transistor may vary in accordance with the channel length. The target channel length is specified by design to meet performance characteristics such as current consumption and device speed. However, normal process variations resulting in a larger channel length (L-effective) will result in a device having low speed and low current, though for all other purposes the device is normal. Conversely, as explained further below, process variations may result in an effective channel length smaller than the target length, thus resulting in a high speed, high current device.
One conventional test measures the static current, i.e., quiescent current (Iddq) to differentiate between good and defective die. Identification of defects is based on the fact that a CMOS circuit does not draw any significant current when in a stable situation. Thus, in a quiescent state, only the leakage current flows, which is often negligible, in some cases on the order of several nanoAmps. A defect such as a short between transistors may cause the quiescent current to increase, indicating a manufacturing defect. Such defects may cause either functional failures or early lifetime failures.
FIGS. 1A–1B are diagrams depicting such fabrication details which may affect the ability of quiescent current testing to identify defects. As illustrated in FIG. 1A, the effective length 102 (L effective) of the channel of the MOSFET device 100 may vary in accordance with process variations in the wafer. The channel forms between the source and drain regions 103. Since speeds of semiconductor devices such as MOSFET transistors are linked to the channel length, differences in effective length affects both the speed behavior of the device and the quiescent current. For example, an effective length 102 of the channel, larger than the target length 104, will result in a lower speed for the device with a lower observed quiescent current. In contrast, as illustrated in FIG. 1B, an effective length 108 that is smaller than the target length 104 will result in a speeded up version of the device 100. That is, the channel formed between the source drain regions 103, results in the high-speed high current device.
Iddq testing is a sensitive technique, able to detect defects in an early stage and offers an alternative to expensive or time-consuming approaches such as burn-in testing. But the downsizing of semiconductor devices to the sub-micron level has made it increasingly difficult to identify and separate outliers from the intrinsic die distribution using conventional quiescent current testing and evaluation. That is, normal process variations will produce an intrinsic probability distribution for a measured parameter, such as the quiescent current. A data point is an “outlier” if it comes from a different probability distribution or from a different deterministic model than the remainder of the data. It is important to effectively screen the dies to identify and separate outliers from the intrinsic distribution, a task made more difficult by the downsizing of the devices.
Many variations of fabrication defects can contribute to the current variations including but not limited to possible lateral shorts between signal lines, vertical shorts (spiking) between layers, or both. Even opens (gaps) on some signal lines, or gaps between vertically stacked layers that are designed to be electrically connected to each other, can lead to higher, rather than lower, current readings.
Excessively low current readings can also be an indication of manufacturing defects, so that in general it is necessary to test the measurement against two limits—one lower limit and one higher limit—before determining that the device under test is defective.
Hence, reliably detecting defective devices is problematic when using conventional methods which measure device current. That is, a device without manufacturing defects may provide an identical current measure as a defective device. For example, a specific defect in a device may draw a large amount of current and be compensated somewhat by the rest of the circuit working correctly, though having a lower intrinsic current.
One conventional method for resolving this issue compares the device under test to some known good ‘reference device’ that was manufactured at the same time and went through the same tools, i.e., a ‘nearest neighbor correlation’. Unfortunately, this method requires post-processing, since only the last device tested on a wafer can be compared inline with the current readings of all of its neighbors.
Accordingly, it is desirable to provide a more effective electrical screening and evaluation method for detecting defects in die.